Date: Thu, 07 Nov 1996 19:16:45 GMT
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<title> Vijay's Home Page </title>
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<h1><center> T.N. Vijaykumar (<!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><a href="http://www.cs.wisc.edu/cgi-bin/finger?vijay">vijay@cs.wisc.edu</a>) <h1>
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<!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><img src="http://www.cs.wisc.edu/~vijay/new.gif"> </center>
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<h2>Professional:</h2>
<h3> Affiliation: </h3> <a href="http://www.cs.wisc.edu">Computer Sciences Department</a>, <!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><a href="http://www.wisc.edu/"> University of Wisconsin-Madison</a>
<h3> Contact:</h3>
Address: Computer Sciences Department, 1210 W. Dayton Street, <!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><a href="http://www.inmarket.com/madison/">Madison</A>, WI 53706 </a> <br>
Phone: 608-262-6587, Fax:  608-262-9777, Email: <!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><a href="mailto:vijay@cs.wisc.edu">vijay@cs.wisc.edu</a><br>

<h3> Advisor:</h3> <!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><a href="http://www.cs.wisc.edu/~sohi/sohi.html">Guri Sohi</a> <br>
<h3> Project:</h3> <!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><a href="http://www.cs.wisc.edu/~mscalar/">The Multiscalar Project</a> <br>
<h3>Education:</h3> 
Doctorate: <!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><a href="http://www.cs.wisc.edu/"> University of Wisconsin-Madison </a>, August 1997 <br>

Undergraduate: <!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><a href="http://dual.iems.nwu.edu/~cnhasan//BITS/bits.html">
Birla Institute of Technology and Science, Pilani</a>, India, 1990 <br>
<h3>Research:</h3>
Compiling for the Multiscalar Architecture (Ph.D. Dissertation)
<li> Distributed Register File Design <br>
<!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><a href="ftp://ftp.cs.wisc.edu/sohi/micro27.ps.Z">
<cite>
The Anatomy of the Register File in a Multiscalar Processor,
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S. Breach, T. N. Vijaykumar, and G. S. Sohi,
27th Annual International Symposium on Microarchitecture (MICRO-27), 1994.

<li> Compiling Register Communication <br>
<!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><a href="ftp://www.cs.wisc.edu//p/multiscalar/vijay/research/writeup/micro96/nonblind.fr.ps">
<cite>
Register Communication Strategies for the Multiscalar Architecture
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</a>
S. Breach, T. N. Vijaykumar, and G. S. Sohi,
Submitted to 29th Annual International Symposium on Microarchitecture (MICRO-29), 1996.

<li> Multiscalar Processors <br>
<!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><a href="ftp://ftp.cs.wisc.edu/sohi/isca95.multiscalar.ps.Z">
<cite>
Multiscalar Processors,
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G. S. Sohi, S. Breach,  and T. N. Vijaykumar,
22th International Symposium on Computer Architecture, 1995.

<li> Scheduling Register Communication <br>
<!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><a href="http://www.cs.wisc.edu/p/multiscalar/vijay/research/writeup/asplos/nonblind.fr.ps">
<cite>
Compiling Register Communication for the Multiscalar Architecture
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T. N. Vijaykumar, and G. S. Sohi,
On going work.
<li> Memory Data Dependence Prediction <br>
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<h2>Personal:</h2>
<h3> My other side ! <!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><a href="http://www.cs.wisc.edu/~vijay/party.gif">
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